1. Field of the Invention
The present invention relates to a method for manufacturing GaAs FET and, more particularly to a manufacturing method of GaAs FET (Field Effect Transistor) using refractory gate of dual structure.
2. Description of the Prior Art
FIGS. 1A to 1F show processes for manufacturing GaAs FET of the prior art using refractory gate. Referring to FIG. 1A, photoresist layer 104 is patterned on a semiconductor substrate 101 as a GaAs wafer in order to define an active region 101a of a semiconductor device, and ions of n type impurity are implanted in the active region 101 of the substrate 101.
In FIG. 1B, after removal of the patterned photoresist layer 104, WSi (tungsten silicon) layer 105 of predetermined thickness is deposited on the substrate 101 by means of sputtering process which is well-known in the art of the invention. Then, photoresist layer 104a is patterned on the WSi layer 105 in order to define a gate of GaAs FET, as shown in FIG. 1C.
Using the patterned photoresist layer 104a as a gate mask, as shown in FIG. 1D, the WSi layer is removed by dry ion-etching process which is well-known in the art, and thus the WSi layer 105a only under the patterned photoresist layer 104a is remained on the active region 101a. Then, the remained WSi layer 105a serves as the gate of GaAs FET.
In addition, after removal of the patterned photoresist layer 104a, photoresist layer 104b is patterned on the substrate 101 in order to define source/drain regions of the substrate 101 as shown in FIG. 1E, and impurity 101b with high density is ion-implanted in the source/drain regions. Finally, ohmic contacts 106a are formed on the source/drain regions.
Manufacturing method of GaAs FET as mentioned above is disclosed in Japanese patent number SHO 60-167475. In this method, gate of GaAs FET is made of tungsten compound such as WSi in order to prevent the gate from reacting on GaAs substrate during annealing process for ion-implant.
However, since material such as WSi has high in electric resistance, problem occurs in operating speed of GaAs FET. Accordingly, the above-mentioned method is largely limited in fabrication of high speed transistor or microwave transistor.
In recent, there is proposed a manufacturing method of GaAs FET in which gate has dual structure in order to reduce electric resistance of the FET. For example, gate has laminated structure in which on WSi layer (or WSiN layer) is deposited with metal such as gold or titanium/gold.
However, since the manufacturing method of the prior art as mentioned above is necessary to use ion-milling process for etching the metal, problems occur in accurate etching and impact of semiconductor substrate by etching ions during etching process.
Moreover, since metal such as gold is low in melting point, formation of gate using gold can not be applicable under circumstance of high temperature, and thus has to use rapidly heating process.